Current trends in the semiconductor and electronics industry require semiconductor devices to be made smaller, faster and require less power consumption. One reason for these trends is that more personal devices are being manufactured that are relatively small and portable, thereby relying on battery power. In addition to being smaller and more portable, personal devices are also requiring increased memory, computational power, and speed. In light of all these trends, there is an ever increasing demand in the industry for integrated circuits which are smaller, faster, and have lower power dissipation. For minimizing integrated circuit power consumption, it is generally desirable for the total power supply voltage to be as low as possible. However, in the case of some types of semiconductor circuits, changes in the power supply voltage must still support stable operation of the circuit.
Semiconductor memory cells can, for example, be characterized as volatile random access memories (RAMs) or nonvolatile read only memories (ROMs), where RAMs can either be static (SRAM) or dynamic (DRAM) differing mainly in the manner by which they store a state of a bit. The basic CMOS SRAM cell generally includes two n-type or n-channel (NMOS) pull-down or drive transistors and two p-type (PMOS) pull-up or load transistors in a cross-coupled inverter configuration, with two additional NMOS select or pass-gate transistors added to make up a standard double-sided or differential six-transistor memory cell (a DS 6T SRAM cell, a 6T SRAM cell, or simply a 6T cell). 8 transistor, 9 transistor, 5 transistor and 4 transistor SRAM cells are also known. Additionally, application specific SRAM cells can include an even greater number of transistors. A plurality of transistors are utilized in SRAM requiring matched electrical characteristics to provide predictable cell switching characteristics, reliable circuit performance, and minimize array power dissipation.
FIG. 1 is schematic of a conventional differential SRAM 6T cell 100. As illustrated, the SRAM cell 100 comprises a data storage cell or latch 102, generally including a pair of cross-coupled inverters, for example, inverter 112, and inverter 114, the latch 102 operable to store a data bit state. FIG. 1 illustrates that the bit is stored in the latch 102 at the data nodes or first and second latch nodes 104 and 106, respectively, having a high or “1” state and a low or “0” state, respectively. Cell 100 also comprises a pair of wordline pass transistors 116, 118 to read and write the data bit between the cross-coupled inverters 112, 114 and bitlines BL 130, BL-bar 132, when enabled by wordline 134.
Respective inverters 112, 114 comprise a p-type MOS (PMOS) pull-up or load transistor Q1 120, Q2 122 and an n-type (NMOS) pull-down transistor Q3 124, Q4 126. Pass gates (e.g., transistors) Q5 116, Q6 118 are n-channel as well, which generally supply higher conductance as compared to p-channel transistors. Pass transistors 116, 118 are enabled by wordline 134 and accessed by bitlines 130, 132 to set or reset the SRAM latch 100. FIG. 1 further illustrates that inverters 112, 114 of the SRAM memory cell 100 are connected together to a high voltage power supply (VDD) terminal 140 and a low voltage power supply (VSS) terminal 150. Both VDD and VSS are generally configured to provide fixed voltage levels, such as 1.2 Volts and 0 Volts, respectively. A VDD for an array is generally referred to as VDDM. Similarly, a VSS for an array is generally referred to as VSSM.
In general, SRAM cells must be stable when accessed for a read operation, yet must be able to be switched from one state to the other for a write operation. Also, unaddressed cells must be stable during a write operation. These somewhat conflicting requirements for stability and write ability must be met over a range of voltages and temperature conditions. What is needed is circuitry that minimizes power consumption and permits stable circuit operations without degrading performance.